Modern integrated circuits (“ICs”) in production require an enormous volume of components. Testing of those ICs requires a large number of test patterns. Transition fault testing has become more prominent, requiring many times more patterns than before. As the chip size and the ratio of logic to be tested per input/output test pin increases dramatically, the amount of data necessary to be supplied by techniques such as automatic test pattern generation (“ATPG”) has become voluminous. Design for test (“DFT”) designers are faced with the challenge of inputting, for each of these large chips, a huge volume of scan test sequences via a minimal number of test pins. Therefore, with ATPG only, the required test time increased and the required amount of tester memory increased, both of which increased cost associated with DFT.
In order to address these challenges, DFT designers have used a technique called Test Compression. Test Compression reduces test data volume and test application time (“TAT”) while retaining test coverage. Using Test Compression, highly compressed test data can be loaded onto the scan chains from low-pin count automated test equipment (“ATE”), using an on-board DeCompressor which decompresses the compressed test data before loading them to a large number of scan chains. After applying the scan chain data to the IC, the response data is then compressed for measurement and comparison. Test Compression recognizes that only a small percentage of scan cells in a scan chain (“care bits”) generated by ATPG are necessary for testing. Test Compression modifies the design to apply the care bits in shorter scan chains, reducing the TAT. The compression ratio generated by Test Compression methods is capable of greatly reducing the test data volume and TAT. For example original data having a volume of 6 Gb and TAT of 20 seconds is, at a 100× compression ratio, reduced by 99% to 60 Mb and TAT of 0.2 seconds.
Test Compression is driven by two structures: a Decompressor and a Compressor (or Compactor). The Decompressor drives the compressed test stimuli onto the IC from the small number of scan-in pins on the ATE to the large number of internal scan channels which feed the logic under test. The Decompressor is designed to allow a continuous flow of stimuli so that it is possible to load the scan chain data for a given test onto the IC and to unload from the IC the previous test response data to the Compressor, all in a single clock cycle. Compression and De-compression logic generally are built using discrete logic gates such as XORs, multiplexers and flip-flops and placed inside a logic module called CoDec which is normally placed in one corner of the IC. Wires transfer test stimuli from the DeCompressor inside the CoDec to the head of the scan channels which may be distributed across the area of the IC. Similarly wires from the tails of the scan channels transfer the test stimuli to the Compressor inside the CoDec.
Wiring all of these connections directly between the scan chains scattered over the surface area of the IC and the decompression and compression logic is referred to as traditional global scan wiring. To reduce the cost of testing ICs DFT engineers try to build more scan chains of shorter length to increase the compression ratio. Higher compression ratios mean that there are more wires running from the CoDec to the heads and tails of the shorter and more numerous scan chains, The additional wiring increases the footprint of the IC and may lead to wiring congestion in the area directly around the decompression logic and compression logic, and the use of extremely long wires to form some of the connections. For compression ratios exceeding 100×, congestion is extreme since there is an extremely large number of wires terminating and originating from a small area of compression logic. As the compression ratios increase, due to better compression algorithms, traditional global placement of logic is no longer appropriate. Other methods have been introduced in efforts to correct the on-board congestion issues associated with compression logic, such as XOR mapping and partitioned Compressor-Decompressors. However, XOR mapping and partitioned Compressor-Decompressor methods are at best incremental improvements.
As chip complexity increases, compression ratios have to increase. However, physical chip layout can prevent implementation of large compression ratios. At a certain point, physical design can become a bottleneck, limiting the total number of wires that can be manufactured in contact with on-board location of the decompression logic and compression logic.